Like many people, I’ve subscribed to Consumer Reports for years.  Generally speaking, I will look at their reviews before venturing out to buy anything that costs more than $50. Sometimes, impulse buying kicks in, and then I rush back to look at the article on what I just bought to see how it fared. That creates positive validation or buyer’s remorse in about the same quantities typically.

I know I’m not alone.  A lot of people won’t make a consumer buying move without first consulting Consumer Reports.  The items with lots of red dots become market leaders and those with lots of black dots, well, don’t. I often reflect on the effectiveness of this system and ponder why it isn’t deployed more broadly.  Why isn’t there a Consumer Reports for semiconductor IP for example?  This is a market whose growth is impeded by uncertain reuse results. There are plenty of tales of missed schedules and difficult design closure due to the unpredictability injected by multi-sourced IP.

Wouldn’t a unified quality standard help this situation?  What if everyone bought IP with full red circles, and no black ones?  Wouldn’t that improve results and encourage more IP vendors to earn a “Recommended” check mark? All this makes sense until you start to look at the implementation details.  What makes Consumer Reports so successful is the clear, unbiased and relevant measurement criteria they apply to create their ratings. If you’re buying tires for your car, for example, there are some fairly clear criteria that are important – how long they last, how well they corner, how safe they are at high speed, etc.

Unfortunately, the standards by which semiconductor IP are judged aren’t as clear or universal. Everyone has their own critical requirements and the definition of success is heavily influenced by the application.  In spite of these challenges, metrics to define IP quality and impartial ways to measure them are emerging. Soft or synthesizable IP presents perhaps the greatest challenge when it comes to judging quality.  Soft IP blocks are basically software, with all the associated configurable behavior of software.  Defining metrics that bracket the usage and integration risks of soft IP is very difficult, but it can be done.

Thanks to the maturing of RTL analysis tools, the quality and completeness of pre-synthesis IP can now be measured with fine detail.  The trick is to know what to look for.  Thanks to many efforts on this front, notably the work TSMC is doing on soft IP qualification, the specific metrics, or rules that must be checked and passed are coming into focus.  This program now has over 15 IP vendors participating, and many, many IPs have been checked.  The rules TSMC applies to check an IP before it is listed on TSMC online include questions such as this:

These questions begin to define a “vocabulary” of soft IP quality; a language everyone can learn to speak.  Has the effort been worth it?  So far, it certainly looks like it.  Significant issues have been uncovered by applying this IP quality “vocabulary” – here is a list of some of them:

• Missing synchronizers on CDC paths causing possible chip function issues
• Data loss on a fast-slow CDC path
• Uncontrolled data path impacting transition fault coverage
• Index out of range, which causes synthesizability issues
• Unconstrained I/O ports leading to poor SDC coverage

This work represents a promising trend in objective measurement for IP quality.  I’m not sure when you’ll be able to pick up your copy of Consumer Reports for Semiconductor IP, but thanks to the efforts of companies like TSMC we can start having a conversation in that direction.

Download the following documents for May 2013:

[gsa-downloads code="1304FUNDING" title="download report (PDF), download excel (XLS)" width="200"]

Methodology (Adobe PDF, 63 KB)

SAN JOSE, Calif. (May 8, 2013) – The Global Semiconductor Alliance (GSA), the voice of the global semiconductor industry, is accepting nominations for its annual GSA awards.  Over the past 19 years, GSA has recognized public and private semiconductor companies that have demonstrated excellence through their success, vision, strategy and future opportunities in the industry. This year’s Award’s Dinner Celebration will be held on Thursday, December 12, 2013, at the Santa Clara Convention Center in Santa Clara, Calif.

The celebration honors the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry. The award categories are as follows:

• Best Financially Managed Semiconductor Company
• Dr. Morris Chang Exemplary Leadership Award
• Most Respected Private Semiconductor Company Award
• Most Respected Public Semiconductor Company Awards
• Outstanding APAC Semiconductor Company Award
• Outstanding EMEA Semiconductor Company Award
• Start-Up to Watch Award

The GSA’s most prestigious award, the Dr. Morris Chang Exemplary Leadership Award recognizes individuals, such as its namesake, Dr. Morris Chang, for their exceptional contributions to drive the development, innovation, growth and long-term opportunities for the semiconductor industry.  Nominations will be accepted until June 3, 2013.  View highlights from previous winners here.

The “Most Respected Private Semiconductor Company Award” is designed to identify the private company garnering the most respect from the industry in terms of its products, vision and future opportunity. GSA’s Private Awards Committee reviews all private semiconductor companies, conducts analysis of each company’s performance and likelihood of long-term success, and provides a list of respectable private companies to be voted on by GSA membership. On-line voting takes place to allow GSA members, including semiconductor companies and partners, to cast a ballot for the private semiconductor company that they most respect.  Nominations are open until June 28, 2013.

GSA’s Private Awards Committee, comprised of members of the Emerging Company CEO Council, venture capitalists and select serial entrepreneurs in the industry, selects up to two winners for the “Start-Up to Watch Award” by identifying the semiconductor company (or companies) that demonstrates the potential to positively change its market or the industry through the innovative use of semiconductor technology or a new application for semiconductor technology.  Nominations will be accepted until June 28, 2013.

As a global organization, the GSA recognizes companies headquartered in the EMEA and APAC regions. Award winners are chosen by the leadership council of each respective region and are semiconductor companies that demonstrate the most strength when measuring products, vision, leadership and success in the marketplace.  Nominations for the Outstanding EMEA Semiconductor Company Award will be accepted until July 12, 2013.

About the GSA Awards Dinner Celebration:

The annual GSA Awards Dinner Celebration is the industry’s premier event. Each year the GSA recognizes companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. The celebration honors the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry. The Awards Dinner Celebration will start at 5:30 p.m. with a networking reception, followed by dinner at 7:00 p.m. The keynote address will be given by Cory Booker, mayor of Newark, New Jersey.

The dinner is made possible by title sponsor TSMC, as well as general sponsors Advantest, Amkor, Broadcom Corporation, Cadence Design Systems, CSR, GLOBALFOUNDRIES, KPMG, Magnachip, UMC and SuVolta. To make reservations to attend the Awards Dinner, please visit:

http://www.gsaglobal.org/events/2013/1212/index.aspx

About GSA:

The Global Semiconductor Alliance (GSA) mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe. www.gsaglobal.org

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This post originally appeared on 3D InCites

There’s probably no more fitting venue for discussing future directions for processing and packaging technology in integrated circuit fabrication than the Computer History Museum in Mountain View, CA. After all, “The mission of the Computer History Museum is to preserve and present for posterity the artifacts and stories of the information age. As such, the Museum plays a unique role in the history of the computing revolution and its worldwide impact on the human experience.” “What’s past is prologue,” right? “The child is father of the man.” Or at least that’s how the English poets (Shakespeare, Wordsworth) would have us see it.

Computer history was our launch pad for the 2013 GSA Silicon Summit, which recognized in its mission statement that “Moore’s Law has transcended computing expectations; however, its promise will eventually reach scalability limitations due to extraordinary consumer demands. Future technology encompasses breakthroughs capable of interaction with the outside world, which the More than Moore movement achieves. Through integrating functionalities that do not scale to deliver cost-optimized and value-added system solutions, this trend holds significant potential for the industry. This event will explore the business and technical factors defining the More than Moore movement, and address how it will yield revolutionary electronic devices.” I always think of the phrase “More than Moore” as being a kind of code that needs decoding or deciphering. “What does ‘More than Moore’ mean?” I might ask you, and you might then respond “What does ‘More than Moore’ mean to you?”

So inspired by computer history, and powered by Google, I set out to find a better answer to the More than Moore question and found this: “Since the early 70’s, the semiconductor industry’s ability to follow Moore’s law has been the engine of a virtuous cycle: through transistor scaling, one obtains a better performance–to- cost ratio of products, which induces an exponential growth of the semiconductor market. … The industry is now faced with the increasing importance of a new trend, ‘More than Moore’ (MtM), where added value to devices is provided by incorporating functionalities that do not necessarily scale according to ‘Moore’s Law’”. (Source: More-than-Moore White Paper, ITRS, 2010. Italics: mine.)

There’s also this, again from the ITRS 2010 White Paper: “The ‘More-than-Moore’ approach typically allows for the non-digital functionalities (e.g., RF communication, power control, passive components, sensors, actuators) to migrate from the system board level into a particular package-level (SiP) or chip-level (SoC) implementation. … The objective of ‘More-than-Moore’ is to extend the use of the silicon-based technology developed in the microelectronics industry to provide new, non-digital functionalities. It often leverages the scaling capabilities derived from the ‘More Moore’ developments to incorporate digital and non-digital functionality into compact systems.” And what might the viable commercial prospects be for deploying ‘More than Moore’ technology? If you’re someone who likes to follow the money (and not just the technology), then, according to the ITRS paper, the MtM money flows from here: “Underlying the evolution of markets and applications, and therefore their economic potential, is their potential in addressing societal trends and challenges for the next decades. Societal trends can be grouped as health and wellness, transport and mobility, security and safety, energy and environment, communication and e-society (this latter term including infotainment).”

The MtM money might even begin flowing from the Internet of Things (IoT).

In a format I would like to see more of at events like this, the GSA Silicon Summit makers-of-opening-remarks turned the helm over, in order, to three well prepared moderators, who led actual conversations with three sets of distinguished panelists without allowing the panelists to resort to PowerPoint slidedecks of their own. This was pure conversation — not the (too) usual present, posture, and feint — with some time allowed for audience questions.

The day was divided into three sessions. Session One, Disruptive Innovation – Enabling Technology for the Connected World of Tomorrow, moderated by Dan Rabinovitsi, Qualcomm, featured panelists from IBM, Freescale, Peregrine, Open-Silicon, and Rambus. Panelists during Session Two, How More than Moore Impacts the Internet of Things, represented Tensilica, ARM, Cisco, and STMIcro. The session was moderated by Ed Sperling, System-Level Design. And Session Three, Integration Challenges and Opportunities, moderated by Bruce Kleinman, GlobalFoundries, comprised panelists from Microsemi, Altera, ASE, Soitec, and SuVolta.

With “More than Moore” as the code phrase of the day, I kept my ear to the ground for decoded responses from the GSA Silicon Summit panelists and moderators, and also from some of the exhibitors and attendees present during the mingle and mix portions of the schedule. I heard such significant tidbits as:

“It’s natural for MEMS and mixed-signal devices, or MEMS and logic devices, to live in a side-by-side (2.5D) world.”

“Organic substrates for 2.5D interposers show great promise for reducing 2.5D interposer costs – look particularly to the work being done by Georgia Tech.”

“If you don’t follow scientific change then what you practice reverts to witchcraft.” (The Rabinovitsi Paradigm.)

“Innovation in packaging may be more relevant than Moore’s Law moving forward.”

“3D packaging is becoming a very exciting technology, with as much relevance as a process node shift.”

“The IoT needs packaging innovations – not Moore’s Law technology progression.”

“FinFET or packaging – where’s the smart money playing? The problem is one of die / device performance versus system performance – and packaging drives system performance.”

“That being said, 3D packaging is not a panacea – basic economics still rule.”

“Seven years from now it will be IoT applications driving the industry – and Moore’s Law progress doesn’t apply to the analog world, hence the need to work on heterogeneous integration / 2.5D / 3D IC.”

“New generations of network-side IC products are only 15% innovation – the other 85% is composed of standard I/O and memory IP. Moving some of that 85% from the board to the interposer or to a 3D stack will be a huge performance improvement – 3D memory integration, for example, is positively disruptive.”

“But doesn’t CMOS integration always win? Monolithic integration, or heterogeneous integration using 2.5D / 3D IC; either way it comes together, no one size fits all.”

“The 28nm process node has a lot to like about it: speed, cost, High Volume Manufacturing (HVM) capability, and IP portability all look good compared to 14nm FinFET.”

“Challenges that need addressing in 2.5D / 3D IC are supply chain related. The current cost structure for 2.5D / 3D is leveraged by materials and processing equipment.”

“Do we currently even have a functioning 3D IC ecosystem?”

“Thermal challenges have kept 3D IC from coming to the mainstream. 2.5D is much better than 3D from a thermal perspective.”

“As for testing 2.5D products, it’s not that different from the testing IBM did for its Multi-Chip Module products. That sounds easy, it’s not, but it does show how you can test, and ship, these products to customers with confidence.”

My take: those comments make for a nifty real-world overlap with the 2010 ITRS white paper on More than Moore, and are a pretty much spot-on reflection of how the Global Semiconductor Alliance promoted the Silicon Summit, as a venue to “… explore the business and technical factors defining the More than Moore movement.”

Computer history in the making, made where computer history resides. The virtuous silicon cycle continues, with a boost from 2.5 / 3D IC.

From Petaluma, CA, thanks for reading. ~ PFW

Second quarter working group meetings kicked off with a flourish. We held both the IP and 3D IC meetings the day before GSA’s annual Silicon Summit. Presentations and minutes can be found here.

IP Licensing Best Practices Explored

The IP working group received an in-depth look at the Semiconductor Committee of the Licensing Executives Society (LES), from committee chair Stefan Tamme, Rambus. This 200 member committee publishes monthly newsletters, webinars, and periodic whitepapers to help ensure semiconductor licensing best practices.

Information presented showed the difference in licensing practices between the High Tech sector and Life Sciences and CEEM (Chemicals, Energy, Environment and Materials) sectors.
For example, 76% high tech IP transactions have peak sales of <$50M royalty base per transaction. In contrast, for Life Sciences IP, 62% of IP transactions have peak sales of >$100M.

Much more information and details are provided in Stefan’s presentation.

Our second presentation, from Philippe Quinio, STMicro, discussed “Managing the IP Sourcing Process”. The presentation discusses the rigor behind STMicro’s sourcing strategy and Make vs. Buy decisions.

Parameters considered include Power, Performance, and Area, as well as Total Cost of Ownership (TOC: development, royalty, risk, etc.). Once the requirement specification is set; any IP that falls below is automatically disqualified. However, you must not stray high above the requirement into over-spec’d / over-engineered regions.

Multiplicative Risks of Delivery, Integration, Adoption, and Potential Legal Challenge are analyzed jointly with development teams, to help ensure requirements are met and trade-offs are properly analyzed. Risks are tabulated and mapped against one another. This allows a pictorial view of all risks values.

Common pitfalls and sourcing trends are covered. In summary, IP Sourcing is business process that must be well managed.

3D IC team continues to grow

The 3D IC group also received two excellent presentations, starting with Bob Patti, Tezzaron, presenting “Fabricating 2.5D, 3D, & 5.5D Devices”. As Tezzaron is currently fabricating 2.5D & 3D devices, in volume, with heterogeneous chips from older technology nodes, Bob shared many insights.

He presented the opportunities and goals of 2.5D/3D, noting that cost savings occur at the system level. The presentation covered several possible assembly and test flows, noting the wealth of opportunity for testing. This poses the question, when, where, and what to test.

In prior design cycles, everything was customer centric; the customer dealt with the fab, OSAT, or other vendors directly. In a 3D IC world, foundry, OSAT, packaging, or test facility must interact directly, posing the thought, what is the customer’s role.

Of course in our brave, new 3D IC world, packaging, cost and complexity increase. For example, die may have to be padded to account for different street sizes at different foundries. Die planarity becomes more critical, so Chemical Mechanical Polishing (CMP) is more critical to ensure bonding to attached die.

Much more detail is available in the presentation, but in conclusion:
Must be aware of what fabs can do and OSAT can’t
Must have the ability to integrate die from different process nodes
Biggest issue is testing trade-offs versus risk
Optimizing the flow will be challenging

Stephen Fairbanks, Certus Semi, presented “3D IC integration and ESD”, by posing the question: Does 3D IC integration make ESD a bigger problem. He then broke the question into three components parts: Are there new ESD threats; are current ESD models and test standards still applicable; are ESD design practices changed due to 3D IC?

New threats include: Backside wafer thinning and additional assembly steps, noting that dry polish is more susceptible to accumulating ESD. New assembly risks include: First TSV contact acting as a discharge path. However, these risks are similar to current Flip-Chip or Wirebond technologies.

Design practice changes, as not every die I/O goes to the outside world, meaning full ESD may not be required on every pin. Only pins with external I/O will experience or be tested for ESD events. Internal I/O pins can be tested for ESD at wafer level, but specialized equipment is required.

CDM will get worse, as a die could pass wafer level test, but fail in a BGA package. Additionally, system level robustness is related to die stack order. CDM currents will find a path between every IC in the stack and external pins. You must consider power domain crossings, similar to designing an SoC.

Failure debug becomes more difficult, as no industry methodology exists for bare die ESD testing. You can’t use Curve Tracer in a 3D stack for HBM/MM testing, and CDM is only for packaged parts (can’t test at wafer level). CDM events are only initiated on external pins, but will flow to every die in stack.

As additional concern occurs as the 3D integrator may not have die design databases for all die to support debugging.

This sort blog can’t do justice to any of these presentations. I encourage you to review the presentation and minutes. Please contact hbeasley@sgaglobal.org with questions.

The workshop’s three sessions focused on common compact modeling actions.   Sessions included: How to consolidate and build consistent simulation hierarchy at all levels of advanced TCAD numerical modeling; Compact/SPICE modeling for Analog / Mixed Signal circuits; and Corner modeling and statistical simulations.

The MOS-AK/GSA speakers discussed: statistical modeling with backward propagation of variance (BPV) and covariance equations (K.-W. Pieper; Infineon); circuit sizing: corner model challenges and applications (M. Sylvester; MunEDA); compact modeling activities in the framework of the EU-Funded “COMON” project (B. Iñiguez; URV); effective device modeling and verification tools (I. Nickeleit; Agilent); modeling effects of dynamic BTI degradation on analog and mixed-signal CMOS circuits (L. Heiss; LTE, TUM);  STEEPER: tunnel field effect transistors (TFETS) technology, devices and applications (T. Schulz; Intel); current and future challenges for TCAD (C. Jungemann; RWTH);  advances in Verilog-A compact semiconductor device modeling with Qucs/QucsStudio (M. Brinson; London Metropolitan University); FDSOI devices bentchmarking (B.-Y. Nguyen; SOITEC); COMON: SOI multigate devices modeling (A. Kloes; THM); COMON: FinFET modeling activities (U. Monga; Intel); COMON: HV MOS devices modeling (M. Bucher; TUC).

The event was accompanied by a series of the software/hardware demos by MOS-AK/GSA industrial partners: Agilent, MunEDA and Tanner EDA. The session technical and software/hardware demo presentations are available for download at: <http://www.mos-ak.org/munich_2013/>

The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Gdynia (https://www.mixdes.org); an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, a winter Q4/2013 MOS-AK/GSA meeting in Washington DC, and a spring Q2/2014 MOS-AK/GSA meeting in London (http://www.mos-ak.org).

About MOS-AK/GSA Modeling Working Group:

<http://www.gsaglobal.org/working-groups/mos-ak-gsa-modeling>

In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK’s purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.

About MunEDA:

<www.muneda.com/>

MunEDA provides leading EDA software technology for analysis, modelling, optimization, and verification of performance and yield of analog, mixed-signal and digital designs.  Founded in 2001 MunEDA has its headquarters in Munich, Germany, with worldwide offices and representations by leading EDA distributors worldwide. MunEDA solutions are in industrial use by leading semiconductor companies in the areas of communication, computer, memories, automotive, and consumer electronics.

About Tanner EDA:

<www.tannereda.com/>

Tanner EDA provides a complete line of software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

MEMS is exciting for medical applications due to micron-sized features, biocompatible materials, ease of electronics integration, and blood level form factor.

Examples of current and future use of MEMS Medical Technology

• MEMS allows cell manipulation, cell level measurements, and cell scaffolding for artificial organs, and detection of circulating cancer cells for very early cancer detection
• MEMS pressure sensors, at 1mm X 1mm, allow catheter insertion to the brain, organs, heart, etc.  Sensors are customized to the procedure and diagnostic needs.
  • Custom market supports use of high value sensors (>$5 versus $0.10)
  • Design reuse is possible, for many elements of an existing design
• Microfluidics devices the size of a microscope slide (25 X 75 mm); a huge size in the MEMS world.  This enables smaller fluid sample size, meaning one can prick the finger as opposed to drawing blood.  This will enable point of care diagnostics.
  • For example, diabetic tools can analyze blood sugar levels in the home
  • Multiple tests to be run from one drop of blood
• Microneedles allow blood sampling without pain to the patient
  • Can draw blood, analyze, and deliver medicine quickly
• FDA has approved CardioMEMS pressure sensors
  • These are battery free, with power from the handheld reader
    • Readout at doctor’s office
  • Used for Aorta stent graft monitoring, pulmonary artery & pressure measurement
  • Delivers mean pressure, systolic & diastolic pressure, heart rate and cardio output
• Edible chips provide a patient pill compliance system.
• Arm worn patches transmits data, via Bluetooth, to a wireless network and then to the doctor.
  • Provides pill authentication and precise dosing
• Argus II Retinal Prosthesis provides 60 pixels of vision to someone with a damaged retina.
  • Enables collision avoidance – previously near blind person can see walls, objects, etc.
• Glaucoma detection made possible via Sensimed Triggerfish IOP monitor
  • Worn for 24 hours, gives doctor information on eye pressure variations.
• Insulin micropumps support discrete wearing, as well as blood sugar detection, analysis, and insulin delivery.

There are of course challenges to use of MEMS in medical applications:

• Packaging – often requires an ASIC, electrical interconnects, mechanical stress management, small form factor, and hermetic seals
• MEMS are square, capillaries are round
• Sterilization – Gamma rays and e-beam can damage electronics and some plastics
• Plastic absorbs ethylene oxide
• Steam can create problems

Summary

• Growing suite of manufacturing techniques
• Hugh opportunities in medical and biotech applications
• Challenges remain, but are being overcome
• There are myriad 50K / year applications.  Hard to get foundry support for small quantities.
• Niche applications often start in hospitals and move to home use (therefore larger volumes)

[gsa-downloads code="Q412FINDOC" title="Download the Q4 2012 GSA Financial Tracker Report" width="250"]

[gsa-downloads code="Q412FINTRACKER" title="Download the Q4 2012 GSA Financial Tracker Spreadsheet" width="250"]

Download the Methodology. (PDF, 24KB)

Download the following documents for April 2013:

[gsa-downloads code="1303FUNDING" title="download report (PDF), download excel (XLS)" width="200"]

Methodology (Adobe PDF, 63 KB)

This past weekend, I needed to replace a Ground Fault Interrupter, GFI for short, outlet in my garage.  The last time I replaced one was several years ago in my sister’s condo.  GFI outlets are a little trickier than standard outlets, but can be swapped out pretty easily.

 When an existing GFI is replaced, it is simply removing a wire at a time and placing on the new GFI terminals.  Depending on the configuration, this could be 3 wires or 5 wires when this outlet feeds additional loads.  A picture of the Old and New GFI is shown below:

Old GFI                                                  New GFI

Looking at the two they look very similar except the lower right hand corner is an LED.  An old piece of IP had a face lift and all directed at helping the user correctly integrate (install) this IP into their home’s power network.  Yes, this is an IP block reused in your home!

I typically read the instructions on GFI outlets and on this updated version a few items changed, all for the better:

1. The LED was added and directly tells a user whether the outlet is ‘hot’ or not.  Unfortunately my old GFI’s did not have this and the circuit breaker box is far from specific on exact breaker/outlet connections.  To ensure that this specific one was shut off, I had to turn off all 15/20A breakers to the house.  Once I installed the new GFI, it was very easy to determine which specific 15A breaker controlled this wiring.  A neat little upgrade to help the user.
2. The second was a very clever change in their product.  In the past, GFI’s came from the factory and you could reset/set the outlet without wiring it up.  You could basically test whether the mechanical switch would toggle between the two states.  Not much good, except it made you feel good.  The new version is reset at the factory and cannot be set until it is correctly wired into your home wiring.

Notice:  I said it must be correctly wired.  If you have the complex 5 wire replacement, 2 of these wires are considered ‘loads’ and must be wired to the ‘load’ terminals.  In my case, the original old GFI was incorrectly wired and just transferring the wires to the new GFI would not work.  I found this out when I had the green LED and then tried to set the GFI.  It would not set nor provide AC to the outlet.  Until I correctly changed the 5 wires (2 white and 2 black) on their correct terminals, the device could not be set.  At least I had the Gnd correctly wired!

This updated IP (GFI outlet) provided “self checking” installation based on how it was constructed and delivered to me.  It provided immediate checks by allowing the device to be set once AFTER it was correctly installed and provided long term value from a simple small LED showing if power was supplied to the outlet.

Given that a very old piece of IP can learn new tricks, here are few thoughts how this might be applied to SIP/VIP/ESIP IP.  All suggestions are focused at easier IP integration and value to the end user.

1.  Subsystems started long ago with Mentor’s USB Subsystem (2006?).  From recent articles, it looks like these are starting to show value to end users.  An obvious method to save time and human error.  Integrating a larger component is easier than integrating all the subcomponents that make up a functioning USB port and validating that they all work as a unit.
2. SIP/VIP combination.  Yes, deliver a block that has all IP (SIP and VIP) already contained in one file.  Similar to SW programs with many underlying modules but a top level program that calls all the others.  User might question how you could trust the same vendor for SIP and VIP products, see #3!
3. Start to have the various industry organizations (i.e. USB IF, SATA SIG, etc) apply ‘certification’ to VIP components.  Both SIP and VIP must be ‘certified’.  This allows early feedback long before expensive implementation and manufacturing are required.  Currently, SIP can be easily tested by a product developer by creating SoC or FPGA depending on the SIP.  This can give the IP consumer some level of comfort but the consumer needs to use IP ‘as is’ and not change it.  Any change increases the risk of not achieving certification/compliance.
   VIP does not have a certification process.  VIP is supposed to be the verification to insure that SIP conforms to a specific standard.  I would encourage these organizations to examine how a ‘certification’ program can be created for VIP.  Maybe use the SIP’s RTL that passed the physical certification testing be used as the golden RTL to test how complete and accurate VIP is?
4. SW/HW platforms that encapsulate an EDA tool that allows users to quickly create designs from a list of qualified IP.  Qualified IP means that the SW understands how to automatically IP to a design and if a user decides to configure a piece of IP, all the IP that are affected by this change are also re-configured to support.  One change replicated throughout the design.  Tensilica (oops, I mean Cadence) has done this with their IP.  It is a mix of EDA SW and IP and any modifications to the ‘processor’ are rippled through all IP views including their SW compiler.  Slick method that has been proven for years.
5. Farther in the future, the delivery of stacked IP systems similar to memory cubes.  Memory cube is the first obvious stacked system IP product, but others will come.  Video, Audio, Encryption, etc are all possibilities for different reasons.  Many will benefit from lower power, higher performance and very easy integration into 2.5/3D package designs.  Some might be for better protection.
6. A better infrastructure that allows automatic updates from IP suppliers to IP consumers whenever bugs have been identified and new releases provided.  Some IP providers have this but why not have ChipEstimate or D&R (or…..) be a central location similar to Amazon (selling books from their inventory as well as from other suppliers).  ChipEstimate might cause concern for other SIP/VIP suppliers since they are owned by Cadence.

Sometimes when you use a functionally different product (GFI outlet), it causes you to think how various aspects might be applied to improve your own products.

Even ‘old’ dogs can teach us new tricks.